1. Field of the Invention
The present invention relates to a solid-state imaging device of, e.g., CCD (Charge Coupled Device) type, a method of manufacturing the solid-state imaging device, and an electronic apparatus including the solid-state imaging device.
2. Description of the Related Art
As one example of solid-state imaging devices, there is a device employing a charge coupled device (CCD). In the CCD solid-state imaging device, a plurality of light receiving sensors are arrayed in a two-dimensional matrix pattern and are each made of a photodiode (PD), i.e., a photoelectric transducer for generating and accumulating signal charges that correspond to the amount of light received by the photoelectric transducer. The signal charges are generated and accumulated based on light signals received from a subject (i.e., an object of shooting), which enters the photodiodes of the plural light receiving sensors. The signal charges are transferred in the vertical direction by vertical transfer registers which are arranged in a one-to-one relation to columns of the light receiving sensors, and are also transferred in the horizontal direction by a horizontal transfer register having the CCD structure. The signal charges transferred in the horizontal direction are output as image information of the subject from an output section including a charge-voltage converter.
As an improvement in the solid-state imaging device of the above-described type, a solid-state imaging device having a plurality of horizontal transfer registers has been recently developed to be adapted for an electronic apparatus having higher resolution, such as a digital high-vision TV (High Resolution Digital Television).
FIG. 8 is a schematic view of principal part of a solid-state imaging device having two horizontal transfer registers, which is disclosed in Japanese Unexamined Patent Application Publication No. 2006-319184. More specifically, FIG. 8 illustrates part of a pixel section 101 of the solid-state imaging device, which includes vertical transfer registers in respective final stages, a first horizontal transfer register 102, and a second horizontal transfer register 104.
The vertical transfer registers include vertical transfer channel regions 105A and 105B which are formed in a substrate 100 and are separated per column by channel stop regions 106, and a vertical transfer electrode 112 formed above the vertical transfer channel regions 105A and 105B to extend in the horizontal direction. As illustrated in FIG. 8, the vertical transfer channel regions 105A and 105B are alternately formed in the horizontal direction.
The first horizontal transfer register 102 is formed at transfer end positions of the vertical transfer registers in respective final stages. The second horizontal transfer register 104 is disposed to extend parallel to the first horizontal transfer register 102. Further, a horizontal-to-horizontal transfer portion 103 is formed between the first horizontal transfer register 102 and the second horizontal transfer register 104.
The first horizontal transfer register 102 and the respectively horizontal transfer channel regions 114 and 115, respectively, which are formed in the substrate 100 to extend in the horizontal direction, and transfer electrodes 107A and 107B and storage electrodes 108A and 108B which are alternately formed above the horizontal transfer channel regions 114 and 115 to extend in the vertical direction as viewed in FIG. 8. Storage regions are formed in parts of the horizontal transfer channel regions 114 and 115 under the storage electrodes 108A and 108B. Also, transfer regions are formed in parts of the horizontal transfer channel regions 114 and 115 under the transfer electrodes 107A and 107B. The transfer electrode 107A is connected to the vertical transfer channel region 105A, and the transfer electrode 107B is connected to the vertical transfer channel region 105B. Further, the storage electrodes 108A and 108B are each formed between the transfer electrodes 107A and 107B in an alternate sequence. A clock signal φ1 is applied to the transfer electrode 107A and the storage electrode 108B, and a clock signal φ2 is applied to the transfer electrode 107B and the storage electrode 108B.
The transfer electrodes 107A and 107B and the storage electrodes 108A and 108B are formed in common to the first horizontal transfer register 102 and the second horizontal transfer register 104, while those electrodes extend obliquely in parts positioned above the horizontal-to-horizontal transfer portion 103.
The horizontal-to-horizontal transfer portion 103 includes a horizontal-to-horizontal channel region 110, a channel stop region 109, and a horizontal-to-horizontal transfer electrode 111 formed above those regions 110 and 109. The horizontal-to-horizontal channel region 110 is formed to extend between the transfer region in part of the first horizontal transfer register 102 positioned under the transfer electrode 107A and the transfer region in part of the second horizontal transfer register 104 positioned under the transfer electrode 107B. The other part of the horizontal-to-horizontal channel region 110 than those transfer regions is formed as the channel stop region 109. A clock signal φHHG is applied to the horizontal-to-horizontal transfer electrode 111.
In the solid-state imaging device having the above-described construction, signal charges held in the vertical transfer channel region 105A of the vertical transfer register in the final stage are first transferred to the transfer region 107A of the first horizontal transfer register 102 upon application of the transfer drive pulse (clock signal) φ1.
The signal charges having been transferred from the vertical transfer channel region 105A are then transferred to the horizontal-to-horizontal channel region 110 of the horizontal-to-horizontal transfer portion 103 upon application of the transfer drive pulse (clock signal) φHGG.
The signal charges held in the horizontal-to-horizontal channel region 110 are then transferred to the transfer region of the second horizontal transfer register 104 under the transfer electrode 107B upon application of the transfer drive pulse (clock signal) φ2. Simultaneously, signal charges held in the vertical transfer channel region 105B are transferred to the transfer region of the first horizontal transfer register 102 under the transfer electrode 107B.
In other words, only the signal charges having been transferred through the vertical transfer channel region 105A are transferred to the second horizontal transfer register 104, while the signal charges having been transferred through the vertical transfer channel region 105B remain within the first horizontal transfer register 102.
As a result, the signal charges in the vertical transfer registers in successive columns are alternately allocated to the first horizontal transfer register 102 and the second horizontal transfer register 104. The signal charges having been transferred to the first horizontal transfer register 102 and the second horizontal transfer register 104 are further transferred as video signals in the horizontal direction.